Powertech Technology targets 2027 launch for panel-level packaging of AI semiconductors

Powertech Technology plans to implement panel-level packaging (PLP) for AI chips by 2027, aiming to increase production efficiency and reduce costs compared to traditional wafer-level methods. While the transition to larger panel formats offers significant scaling potential, the technical feasibility of maintaining high yields for advanced AI silicon remains unproven at this scale. This development signals a potential shift in semiconductor supply chain manufacturing standards to meet surging AI hardware demand.